1. Field of the Invention
The present invention generally relates to random access memory (RAM) assemblies and, more particularly, to dynamic redundancy for RAM assemblies using reduced specification RAM chips where only bad cells or locations are replaced on a real time basis rather than replacing an entire quadrant of a RAM chip.
2. Background Description
In the manufacture of dynamic random access memories (DRAMs), individual chips are tested as part of the manufacturing process. Inevitably, some of the chips will fail certain tests. Rather than simply discarding these chips, they are identified as reduced specification memory ("yield loss"). l)RAM chips are typically composed of a plurality of banks of memory arrays, and if a failure occurred in, say, two banks of an eight bank l)RAM chip, the chip would be identified as a three quarter reduced specification memory.
DRAM shortages, coupled with a never-ending supply of reduced specification memory, drive the need to re-use reduced specification memory in computer applications. Current industry practices are to utilize reduced specification DRAM chips as "partially good" RAM chips, generally in the data dimension, and use additional DRAM chips to replace defective bits. This technique, while making use of "partially good" chips, is generally wasteful in that a RAM chip with only one or more cells bad will be downgraded to a three quarter or one half good device, rather than simply replacing the defective cells.